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uart
- 该源码包是uart串口协议的verilog语言模型，主要包括了3个部分：波特率产生模块，uart接收模块，uart发送模块。(The source package is UART serial protocol Verilog language model, including 3 main parts: baud rate generation module, UART receiver module, UART transmission module.)
uart
- 嵌入式串口通讯，采用verilog编写，在altera开发板上运行(Embedded serial communication, written using Verilog, altera development board on the run)
UART
- verilog IO模拟串口,用IO模拟uart进行串口通讯，无需硬件串口(Verilog io analog serial port, using io simulation UART serial communication, no hardware serial port)
uart
- UART 功能模块，Verilog，简单实用(UART function module, Verilog, simple and practical)
FPGA实现串口解析
- 用verilog语言不同的编写方式来 实现各种复杂串口通讯(use the verilog to uart)
UART
- 使用verilog实现串口通信功能，modesim仿真成功(Using Verilog to achieve serial communication function, modesim simulation success)
UART
- 用Verilog实现的全局异步接收发送机，在quartus平台测试成功。(Use Verilog implementation of global asynchronous receive transmitter in quartus platform test successfully)
uart
- 基于verilog的fpga串口通信,rx,tx.两根线(Basend on verilog fpga uart tong xin)
UART
- UART loopback测试实例，接收PC端发送的UART数 据，原数据返回给PC端，即loopback功能(The UART loopback test instance receives the number of UART sent by the PC side According to the original data returned to the PC side, that is, the loopback function)
UART-master
- FPGA Based UART in Verilog
Verilog_uart
- 锆石科技 用Verilog实现uart通信，文件包括模块和顶层文件，直接解压缩在quartus上编译即可。(Zircon technology Verilog with uart communication, the file includes the module and the top file, the direct decompression can be compiled on the quartus.)
UART1
- 基于Verilog的串口RS232控制器(RS232 controller of serial port based on Verilog)
uart-master
- verilog语言实现URAT串口通信，便捷开发(Implementation of various basic circuits in digital circuits with Verilog language)
uart
- 一个具有固定波特率的 UART 串口收发器，可以实现 串口收发器，可以实现 9600 波特率的串口通信， 能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication, and can communicate with PC
eetop.cn_uart 源码 (Verilog)
- Verilog编写的UART通信模块，比较清晰(UART model wrote by Verilog)
VERILOG_UART
- Simple implementation of UART on Verilog
UART
- Verilog写的UART 协议。可用于FPGA RS232接口实现。(The UART protocol written by Verilog. It can be used for the implementation of the FPGA RS232 interface.)
uart_test_Verilog
- 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configura
Receiver_spartn6_v1
- Implement design of UART receiver in verilog
uart
- uart串口FPGA实现示例 example(uart serial interface example)